wafer.space Community - Using gf180mcu_ocd

@Tim Edwards BTW, basic testing seem to show that IO library works in silicon

tnt changed the channel name: Using gf180mcu_ocd_io in LibreLane 04/22/2026 06:53

@tnt : What kind of "basic testing"?

Well, they're fed 3.3v on both Vio and Vcore and they pass data between the inside and the outside of the chip

What chip was that? I thought I was the only one using my I/O library.

That's the extend of the testing that will be done at the factory until I get my hands on the chips.

12:05

We have a version of the tiny tapeout GF 0.2 that uses your library. (edited)

Oh, wow, I didn't know that. Nice!

Hopefully by end of next week I'll be able to make actual delay / rise / fall measurements and IV curves and all that stuff with different Vio and Vcore .

I don't think I ever actually tested operation with Vio at 3.3V.

I simulated that case and it's behaving just fine AFAICT. Pretty much same results as the original GF pads at 3.3v.

12:09

Some of your dies should be on their way to you so if you have bonding capability locally you can test those too

Looking fwd to seeing the 3.3V SRAM results

@tnt - The first package of Tiny Tapeout bonded die went out to you today.

1

@Tim 'mithro' Ansell Got a tracking number ?

tnt

@Tim 'mithro' Ansell Got a tracking number ?

I would be able to get you one if the fedex website wasn't so terrible...

14:23

It's ok, I guess I should eventually get a notification by mail.

14:23

Better not share it publically anyway ..

@Tim Edwards Did a bit more testing and they seem to perform just fine at 3.3V Got rise time of 2 ns and fall time of 1 ns ( not sure of the load, it's a test pcb + scope probe so probably in the 20~30 pF range ). And the output still looked pretty square outputting a 75 MHz clock. TBH they work better than the sky130 and IHP ones

(edited)

The sky130 pads are over-designed and the IHP pads are under-designed, so that's not entirely surprising. Are you planning any tests at 5V?

@Tim Edwards Yes I am. But the breakout I have is unsuitable for 5V test ATM, so I need to wait until I get one where I can set Vio to what I want.

16:01

BTW there are diodes between Vcore and Vio, so Vio needs to come up first

I'm not sure if I looked specifically for diodes between the power supplies. Would there happen to be a forward-biased diode from Vio to Vcore? That would be a big problem for running the I/O voltage at 5V.

No, it's forward biased from Vcore to Vio. So must have Vio >= Vcore

In what cell(s)? A quick check of the netlist for D entries shows only diodes between pad and power, and between ground and power.

Ah ... that I haven't searched yet, I can just tell you I see it in the silicon

Probably some indirect path like through a pullup resistor or something.

I was feeding 3.3V to Vcore and I haden't power Vio yet and still the IO were powered through it ...

I'll have to go analyze that one.